In recent years, in design and manufacturing of chips, an increasing number of chips, e.g., integrated circuits, such as LSIs (Large Scale Integrations), actually manufactured, fail to satisfy the performance reference values, i.e., specs, defined in the design phase, due to the scale-down of processes. More specifically, an increasing number of chips have path delay values (real values) actually obtained in the real chips, that is deviated from prediction values of path delays of the chips designed calculated using a simulation tool or like during the design phase. As a result, such actual chips often fail to satisfy the spec defined during the design phase.
This necessitates delay tests on actual chips during design and manufacturing of chips. FIG. 16 is a flowchart schematically illustrating a typical design and manufacturing procedure of chip, including a delay test. As depicted in FIG. 16, after a chip is designed (Step S1), a prototype chip of the designed chip, i.e., an actual chip, is fabricated (Step S2). A delay test is performed on the actual chip (Step S3) to determine whether the result of the delay test satisfies a predetermined spec.
The result of the delay test satisfies a predetermined spec (the YES route in Step S3), actual chips are started to be manufactured based on the design made in Step S1 (Step S4). Otherwise, the result of the delay test satisfies a predetermined spec (the NO route in Step S3), a failure analysis, i.e., a delay cause analysis is performed based on the result of the delay test (Step S5). The flow returns to Step S1, wherein a chip is redesigned in accordance with the analysis result in Step S5.
A delay test is a test for identifying the clock frequency or clock cycle at which the tested actual chip can operate, and the following operations are carried out in a single delay test. Note that FIG. 17 is a drawing illustrating an example of circuit configuration on a test target actual chip for illustrating a typical delay test. In FIG. 17, reference symbol 101 indicates a flip flop (FF), which is an input-side resistor on an actual chip, while reference symbol 102 indicates another flip flop (FF), which is an output-side resistor on the chip, and a combinational circuit including various types of gates is arranged between the FF 101 and the FF 102. The connections within the combinational circuit are specified based on a net list of a circuit to be designed.
Firstly, two test vectors are provided, and a signal based on inputs of the two test vectors are propagated from the input-side FF 101 to the output-side FF 102 of the actual chip. After the first test vector is input, the second test vector is input to the input-side FF 101 of the actual chip by issuing two clocks having a certain time interval, which is captured in the output-side FF 102. The value in the output-side FF 102 is compared against an expected value (prediction value) expected to be obtained at the output-side FF 102 after the two test vectors are input to determine whether these values are matched.
If they match, after the predetermined time interval is incrementally reduced, such as with a decrement of 20 MHz, for example, two test vectors are input again to determine whether the value at the output-side FF 102 matches the expected value. The procedure is repeatedly executed until the value at the output-side FF 102 and the expected value mismatch. The time interval (cycle) immediately before the mismatch occurs is obtained as a result of the delay test, i.e., the measurement value of the delay time in the test.
It is determined that whether the obtained measurement value satisfies a predetermined spec. If it is determined that the predetermined spec is satisfied, i.e., the prototyped actual chip operates normally at the targeted clock cycle, actual chips are started to be manufactured (Step S4), as described above. Otherwise, if it is not determined that the predetermined spec is satisfied, a delay cause analysis is performed based on the result of the delay test (Step S5) and redesign is made (Step S1).
In Step S5, references to the measurement value of the delay time obtained in the delay test, and the path on which a signal propagates through the input of the two test vectors in the delay test, i.e., activated path are made. Then, an analysis on the delay cause is made, based on the measurement value and the activated path. Hereinafter, such an “activated path” is referred to as an “activation path”. The activation path is calculated and identified based on a net list of the circuit to be designed and values of two test vectors input in the delay test. In FIG. 17, activation paths are drawn in thick lines.
In addition, a technique called “speed path analysis” is used as a failure analysis technique in Step S5, for example. In such a speed path analysis, if the number of activation paths during the delay test is one, the measurement value of the delay time obtained in the delay test is assigned to that activation path for analysis. Alternatively, if the number of activation paths during the delay test is two or more, in other words, two or more activation paths are connected to a single output-side FF via a multiple-input cell, one of the two or more activation paths is selected (they are narrowed down to one). This narrowing down is performed by selecting one activation path having the maximum delay time from the input-side FF to the multiple-input cell delay time, among the two or more activation paths, for example. After the measurement value of the delay time obtained in the delay test is assigned to the one narrowed-down activation path for performing the analysis.
The above-described deviation between a prediction value of a path delay and a path delay value obtained at an actual chip (actual value) is caused by a phenomenon that has been modeled only in a simplified manner, but has become noticeable due to the scale-down of processes. As one cause of such “deviation”, a phenomenon called multiple-input switching (MIS) in a multiple-input cell has attracted great deal of attentions.
A multiple-input switching is a phenomenon in which, when multiple signals are simultaneously or substantially simultaneously input to a multiple-input cell, such as a NAND or NOR, for example, the delay time of the output from the multiple-input cell in response to the input is shortened or lengthened than an assumed value. Such a multiple-input switching will be described with reference to FIG. 18A to FIG. 18D, using an example of a 2-input NAND gate.
At the NAND gate depicted in FIG. 18A, two input signals which transition from 0 to 1 are input at the timing AA and AB, and an output signal which transitions from 1 to 0 is output at the timing AOUT. FIG. 18B is a graph indicating the relationship of the input time difference SAB (=AA−AB) between the two input signals and the delay time “delay” at the output from the NAND gate, when the signal transition depicted in FIG. 18A occurs. As depicted in FIG. 18B, it has been well-known that the output delay time “delay” is increased by 16% at maximum than the assumed value DA or DB when the two input signals are substantially simultaneously input to the NAND gate and the output signal falls from 1 to 0.
At the NAND gate depicted in FIG. 18C, two input signals which transition from 1 to 0 are input at the timing AA and AB, and an output signal which transitions from 0 to 1 is output at the timing AOUT. FIG. 18D is a graph indicating the relationship of the input time difference SAB the delay time “delay” at the output from the NAND gate, when the signal transition depicted in FIG. 18C occurs. As depicted in FIG. 18D, it has been well-known that the output delay time “delay” is reduced by 34% at maximum than the assumed value DA or DB when the two input signals are substantially simultaneously input to the NAND gate and the output signal rises from 0 to 1.
Here, the assumed value DA is the value of the output delay time “delay” at the region in which the input timing AA in a first path (on the side of A) is sufficiently slower than the input timing AB in a second path (on the side of B), i.e., the region in which the delay in the first input path is dominant (A dominant). In contrast, the assumed value DB is the value of the output delay time “delay” at the region in which the input timing AB in the second path is sufficiently slower than the input timing AA in the first, i.e., the region in which the delay in the second input path is dominant (B dominant). The input timing AA or AB of each path corresponds to the delay time from input-side FF to the NAND gate on that path.
When a multiple-input switching as described above are considered, the following two scenarios (1) and (2) are possible when two or more paths inputting to one multiple-input cell are activated. As used herein, a delay time from the input-side FF to the multiple-input cell in an activation path is referred to as a “path delay value”.
(1) A scenario in which one activation path is dominant. More specifically, one path delay value of two or more activation paths is significantly greater than path delay values of other activation paths, and the one activation path determines a measurement value obtained in a delay test.
(2) A scenario in which a multiple-input switching is occurring. More specifically, signals of two or more activation paths are input at the same or substantially same timing. In other words, the path delay values of the two or more activation paths are the same or substantially same, and all of the two or more activation paths determine a measurement value obtained in a delay test.
In conventional failure analysis techniques, the two or more activation paths are narrowed down to one path in both of the above scenarios (1) and (2), and the measurement value is assigned to that one narrowed-down activation path for performing a failure analysis. In the above scenario (1), the narrowing-down causes is not problematic since that one activation path is dominant. In contrast, in the above scenario (2), that is, a multiple-input switching is occurring, although all of the two or more activation paths possibly affect the measurement value, a failure analysis is performed on a single activation path that has the greatest path delay value. As a result, information on the multiple-input switching is discarded, and any determination as of occurrence of a multiple-input switching or any consideration on the effect of a multiple-input switching during an analysis cannot be made, which may make the failure analysis inaccurate.
In addition to the failure analysis technique described above, another technique is well-known in which a cell causing a multiple-input switching is identified based in measurement value obtained in a delay test. This technique, the sensitivity of each cell in a combinational circuit is determined by using fitting computation to a linear method using the Monte Carlo technique, and a cell causing a multiple-input switching can be identified based on the determined sensitivity. However, the computation processing of this technique takes great deal of time.    Patent Reference 1: Japanese Laid-Open Patent Application No. H02-90267    Patent Reference 2: Japanese Laid-open Patent Publication No. 2000-305966    Non-Patent Reference 1: P. Bastani, N. Callegari, Li-C. Wang, et al., “Statistical Diagnosis of Unmodeled Systematic Timing Effects”, DAC'08, 22.1, pp. 355-360    Non-Patent Reference 2: P. Bastani, K. Killpack, et al., “Speedpath Prediction Based on Learning from a Small Set of Examples”, DAC'08, 12.3, pp. 217-222    Non-Patent Reference 3: T. Fukuoka, A. Tsuchiya, et al., “Statistical Gate Delay Model for Multiple Input Switching”, ASP DAC'08, 4A-1, pp. 286-291    Non-Patent Reference 4: K. Killpack, C. Kashyap, et al., “Silicon Speedpath Measurement and Feedback into EDA flows”, DAC2007, 22.2, pp. 390-395